Reset detection circuits are used to perform voltage drop detection and reset operation (JP 2005-316594A, for example). The reset detection circuit detects that a voltage VDD applied to a logic circuit and a RAM provided in a semiconductor integrated circuit has dropped below a reset voltage for the logic circuit or a guarantee voltage for retaining the charge of the RAM (RAM retention voltage). It then resets the logic circuit or performs other like operations, when this detection takes place.
A conventional reset detection circuit 100 includes, as shown in FIG. 5, a comparator 101, a reference voltage circuit 102, and voltage dividing resistors 103, 104.
The comparator 101 operates under power supply from a power supply line to which a voltage 5VIN of a 5V power source, formed by stepping down a 12V voltage generated by an in-vehicle battery or the like, is applied. Similarly, the reference voltage circuit 102 operates under power supply from the power supply line to which the voltage 5VIN of the 5V power source, formed by stepping down the voltage of 12V of the in-vehicle battery or the like, is applied, and generates a reference voltage Vref. The voltage dividing resistors 103, 104 are used to divide the voltage VDD of a power supply line for power supply to a logic circuit and RAM, and generate a voltage in proportion to the voltage VDD. The reference voltage Vref formed by the reference voltage circuit 102 is inputted to the non-inverting input terminal of the comparator 101, and the potential between the voltage dividing resistors 103, 104 is inputted to the inverting input terminal of the comparator 101.
In this reset detection circuit 100, the potential between the voltage dividing resistors 103, 104 is compared with the reference voltage Vref by the comparator 101, which determines whether the voltage VDD is equal to or higher than a reset voltage and a RAM retention voltage.
In this reset detection circuit 100, the following relation is so set that it is set as VDD>V-RST>V-MIN: the relation between the voltage VDD, the logic circuit reset voltage and RAM retention voltage V-RST, and the minimum operating voltage V-MIN of a circuit that uses the voltage 5VIN of the 5V power source as power supply voltage. For examples, these are so set that VDD=2.5V, V-RST=2.0V, and V-MIN=1.8V.
For this reason, it can be determined at the reset detection circuit 100 whether the voltage VDD is equal to or higher than the reset voltage and RAM retention voltage V-RST in all the following cases: when the power supply is started, when the battery is instantaneously disconnected, when the voltage VDD falls due to a surge, and when the power supply is stopped.
FIG. 6 is a timing diagram showing the situations that occur when power supply is started at time t1, when the battery is instantaneously disconnected at time t2, when the voltage VDD falls due to a surge at time t3, and when power supply stops at time t4.
As shown in this figure, the voltage VDD rises at time t1 after the voltage 5VIN of the 5V power source rises, and it rises to a desired potential. If the voltage 5VIN becomes equal to or higher than the minimum operating voltage V-MIN at this time, the operation of the comparator 101 that uses the voltage 5VIN as power supply voltage cannot be guaranteed. For this reason, the reset detection circuit 100 cannot detect that the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST. However, this is acceptable, because the voltage VDD is formed by stepping down the voltage 5VIN inside or outside a semiconductor integrated circuit and the voltage 5VIN rises earlier than the voltage VDD. For this reason, the reset detection circuit 100 can detects that the voltage VDD becomes equal to or higher than the reset voltage and RAM retention voltage V-RST when the power supply is started.
When the battery is instantaneously disconnected at time t2, the voltage 5VIN lowers with decrease in the battery voltage and the voltage VDD also lowers at the same time. Therefore, the voltage VDD becomes lower than the reset voltage and RAM retention voltage V-RST before the voltage 5VIN becomes lower than the minimum operating voltage V-MIN. For this reason, also, when the battery is instantaneously disconnected, the reset detection circuit 100 can detect that the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST.
When the voltage VDD falls due to a surge at time t3, the voltage 5VIN is not lowered. Therefore, the reset detection circuit 100 can detect that the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST. Surge is instantaneous voltage fluctuation due to noise or the like, and reset can also be triggered by a surge depending on a time constant or the like.
Also, when the power supply stops at time t4, similarly with instantaneous disconnection of the battery, the voltage VDD becomes lower than the reset voltage and RAM retention voltage V-RST before the voltage 5VIN becomes lower than the minimum operating voltage V-MIN. Therefore, the reset detection circuit 100 can detect that the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST.
In recent years, as semiconductor processes are miniaturized, the voltage VDD used as power supply for a logic circuit has been more and more lowered. Also, the reset voltage and RAM retention voltage V-RST has also been more and more reduced. On the other hand, the battery voltage and 5V power supply systems are used as the power supply for printed circuit boards mounted with a semiconductor integrated circuit and the like, and a 5V power source is also used for interfaces between a semiconductor integrated circuit and a printed circuit board.
For this reason, the following relation is often set as V-MIN>VDD>V-RST: the relation between the voltage VDD, the logic circuits reset voltage and RAM retention voltage V-RST, and the minimum operating voltage V-MIN of a circuit that uses the voltage 5VIN of a 5V power source as power supply voltage. For example, these are so set that VDD=1.5V, V-RST=1.2V, and V-MIN=1.8V.
In this instance, the reset detection circuit 100 constructed as illustrated in FIG. 5 cannot accurately detect that the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST in the following cases: when the power supply is started, when the battery is instantaneously disconnected, and when the power supply is stopped.
FIG. 7 is a timing diagram showing the situations that occur when the power supply is started at time t1, when the battery is instantaneously disconnected at time t2, when the voltage VDD falls due to a surge at time t3, and when the power supply stops at time t4, under a condition of V-MIN>VDD>V-RST.
When the power supply is started at time t1, a rise of the voltage VDD from the low level to the high level is completed before the voltage 5VIN becomes equal to or higher than the minimum operating voltage V-MIN because of the lowered voltage VDD. For this reason, the operation of the comparator 101 that uses the voltage 5VIN as the power supply voltage cannot be guaranteed. Therefore, the reset detection circuit 100 cannot detect that the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST.
In case of the instantaneous disconnection of the battery at time t2, when the voltage 5VIN lowers in conjunction with lowering of the battery voltage, the voltage VDD also lowers simultaneously. However, the voltage 5VIN becomes lower than the minimum operating voltage V-MIN before the voltage VDD becomes lower than the reset voltage and RAM retention voltage V-RST. For this reason, also, when the battery is instantaneously disconnected, the reset detection circuit 100 cannot detect that the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST.
With respect to a fall of the power supply from the high level to the lower level at time t4, similarly, the voltage 5VIN becomes lower than the minimum operating voltage V-MIN before the voltage VDD becomes lower than the reset voltage and RAM retention voltage V-RST. For this reason, also, when the power supply stops, the reset detection circuit 100 cannot detect that the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST.
Problems may arise if it cannot be accurately detected that the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST in the following cases, as described: when the power supply is started, when the battery is instantaneously disconnected, or when the power supply stops. For example, the logic circuit or RAM cannot be reset even though the voltage VDD has become lower than the reset voltage and RAM retention voltage V-RST.